Integrated HBM2 PHY and Memory Controller provide validated,
standards-compliant memory subsystem with superior signal integrity and
reliability
SUNNYVALE, Calif.--(BUSINESS WIRE)--
Rambus
Inc. (NASDAQ: RMBS), an innovator in semiconductor and IP products,
today announced validated interoperability between its HBM2
PHY and Northwest
Logics’ HBM2 Memory Controller Core. The solution builds on the
growing ecosystem of Rambus partner products that interoperate with its
latest HBM2 PHY IP core. The combined HBM2 solution is designed to
support high-performance networking and server applications in the data
center and communications markets that require the maximum amount of
bandwidth available through HBM2.
“Our work with Northwest Logic gives Rambus the functionality to provide
a verified solution that reduces the engineering workload and time to
market for chip designers,” said Luc Seraphin, senior vice president and
general manager of the Rambus Memory and Interfaces Division. “As Rambus
extends its footprint in PHY support for leading-edge technologies,
collaborative interoperability is essential for our end customers that
demand early adoption. Memory interfaces are increasingly important in
today’s new workloads, and the combination of the Rambus HBM2 PHY and
Northwest Logic HBM2 Memory Controller core is a natural fit to support
customer demands on both sides.”
The Northwest Logic HBM2 Memory Controller Cores are optimized for use
in both ASICs and FPGAs, and support full-rate, half-rate and
quarter-rate operations. The cores provide a solution that can be
configured to exact customer requirements, are silicon-proven and are
verified with the Rambus HBM2 PHY.
“Our HBM2 Memory Controller Core has been successfully deployed in a
wide variety of customer systems demonstrating high reliability and
performance,” said Brian Daellenbach, president of Northwest Logic. “We
are excited to offer a complete HBM2 solution with Rambus ensuring our
customers achieve the best possible combined memory solution for their
high data demands.”
The Rambus HBM2 PHY and Northwest Logic HBM2 Memory Controller are each
fully JEDEC compliant to the HBM2 standard, allowing the PHY and memory
controller to interoperate. The Rambus HBM2 PHY is a high-performance
memory IP core that features reduced power consumption and a small form
factor. It combines 2.5D packaging with a wider interface at a lower
clock speed, delivering higher efficiency and lower power consumption
compared to other memory solutions on the market. For additional
information on Rambus HBM2 PHY solutions, please visit https://www.rambus.com/memory-and-interfaces/ddrn-phys/hbm/
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About Rambus Memory and Interfaces Division
The Rambus Memory and Interfaces Division develops products and services
that solve the power, performance, and capacity challenges of the
communications and data center computing markets. Rambus enhanced
standards-compatible and custom memory and serial link solutions include
chips, architectures, memory and SerDes interfaces, IP validation tools,
and system and IC design services. Developed through our system-aware
design methodology, Rambus products deliver improved time-to-market and
first-time-right quality.
About Rambus Inc.
Rambus creates innovative hardware and software technologies, driving
advancements from the data center to the mobile edge. Our chips,
customizable IP cores, architecture licenses, tools, software, services,
training and innovations improve the competitive advantage of our
customers. We collaborate with the industry, partnering with leading
ASIC and SoC designers, foundries, IP developers, EDA companies and
validation labs. Our products are integrated into tens of billions of
devices and systems, powering and securing diverse applications,
including Big Data, Internet of Things (IoT), mobile payments, and smart
ticketing. At Rambus, we are makers of better. For more information,
visit rambus.com.
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Source: Rambus Inc.